Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Short-circuit power driven gate sizing technique for reducing powerdissipation

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here     

K- and Q-bands CMOS frequency sources with X-band quadrature VCO

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-/spl mu/m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To have more harmonic power, a frequency doubler with pinchoff clipping is used without any buffers or dc-level shifters. The QVCO has a low phase noise of -118.67 dBc/Hz at a 1-MHz offset frequency with a 1.8-V power supply. The transistor size effect on phase noise is investigated. The frequency doubler has a low phase noise of -111.67 dBc/Hz at a 1-MHz offset frequency is measured, which is 7 dB higher than a phase noise of the QVCO. The doubler can be tuned between 19.8-22 GHz and the output is -6.83 dBm. A fourth-order frequency multiplier, which is used to obtain 40-GHz outputs, shows a phase noise of -102.0 dBc/Hz at 1-MHz offset frequency with the output power of -18.0 dBm. A large tuning range of 39.3-43.67 GHz (10%) is observed.     

Diagnosis of tapping operations using an AI approach

On-line diagnosis of the machining operations is essential because it can prevent potential problems caused by abnormal conditions. So far, little research has been done for the on-line diagnosis of tapping operations. However, tapping is a very important machining operation. And the on-line diagnosis is essential. In this work, an artificial neural network was utilized for the diagnosis of the tapping operation. The input vector for the neural network is obtained by processing the signals of the thrust, torque, and lateral forces during the tapping operations. A total of ten indices were used in the input layer of the network. The output of the artificial neural network provides the tapping states. Five different tapping states were investigated: normal operation, tap wear, misalignment, oversize hole, and undersize hole. The weights and thresholds of the artificial neural network can be modified by the generalized delta rule. Experimental results showed that diagnosis of tapping operations through an artificial neural network can reach a success rate of over 95%.     

Distributed Multirobot Exploration and Mapping

Efficient exploration of unknown environments is a fundamental problem in mobile robotics. We present an approach to distributed multirobot mapping and exploration. Our system enables teams of robots to efficiently explore environments from different, unknown locations. In order to ensure consistency when combining their data into shared maps, the robots actively seek to verify their relative locations. Using shared maps, they coordinate their exploration strategies to maximize the efficiency of exploration. This system was evaluated under extremely realistic real-world conditions. An outside evaluation team found the system to be highly efficient and robust. The maps generated by our approach are consistently more accurate than those generated by manually measuring the locations and extensions of rooms and objects.     

Reliability of a k-out-of-n: G system with common-mode outages

This paper presents the model of a k-out-of-n: G system with common mode outages. The objective is to analytically derive the mean operating mode between failures for a non-repairable component system. The average system failure time and the system availability are also considered. Then, the model is extended to a system with repairable components and unrestricted repair, in which service times are exponentially distributed.